A complementary metal-oxide-semiconductor (CMOS) IC device may use a gate oxide film having a small thickness. Hence, a CMOS IC device may be vulnerable to an electrostatic discharge (ESD).
ESD may occur when electrostatic charges are transferred between two objects having different electrostatic potentials.
Since a large amount of energy may be instantaneously emitted in a short time of about 150 ns or less due to the ESD, the CMOS IC device may be damaged. In particular, the ESD may be an important factor related to reliability of a nano IC device.
Due to the ESD, thermal breakdown of silicon may occur, a metal contact may be fused due to instantaneous high current, or insulation breakdown of a gate oxide film may occur due to a high voltage and excessive stress, thereby causing failure of an IC chip.
In human body model (HBM) ESD stress, the ESD standard of a commercially available IC product may be 2 kV, and in machine model (MM) ESD stress, the ESD standard may be 200 V.
In order to avoid such ESD stress, an ESD protection circuit may be mounted on the chip. Accordingly, the ESD stress may be avoided and the IC chip may be protected.
FIG. 1 is a circuit diagram showing a related art ESD protection device. As shown in FIG. 1, a grounded gate NMOS (GGNMOS) may be used as the ESD protection circuit.
The ESD protection circuit may have a large size. However, if a size of the protection circuit is large, a parasitic component may increase in an input terminal.
Referring to FIG. 1, the related art ESD protection circuit 12 may be connected between pad 10 and internal circuit 16.
Internal circuit 16 may be connected to pad 10 via input buffer 14 between VDD and VSS. Input buffer 14 may include PMOS transistor P1 and NMOS transistor N1 that may be connected in an inverter structure between VDD and VSS.
The related art ESD protection circuit 12 may include a plurality (eight to ten) of GGNMOSs M11, M12, M13, M14, M15, M16, M17 and M18, which may be arranged between pad 10 and ground VSS in parallel. The gates and the sources of the GGNMOSs may be connected to VSS via a substrate (or a well) and the drains thereof may be connected to pad 10.
Accordingly, the GGNMOS may have a structure including an npn bipolar transistor in which the source, the substrate, and the drain may be connected. Since the npn bipolar transistor may be a bulk device unlike an MOSFET which may be a surface device, a large amount of current may be consumed in an ON state.
When the IC chip normally operates, that is, when a nominal voltage is applied via pad 10, the GGNMOSs may be turned off. Accordingly, a gate voltage Vgs may be 0 and current may not flow between the drains and sources of the GGNMOSs.
When ESD occurs in the IC chip, a high electric field may be applied to the drains of the GGNMOSs via pad 10, and impact ionization or avalanche may occur in a reverse-biased drain/substrate junction. A voltage across a substrate resistor may increase a base-emitter voltage of the npn bipolar transistor. As a result, the npn bipolar transistor may be turned on.
When the ESD voltage has a positive (+) polarity, a parasitic npn bipolar transistor included in the GGNMOSs may form a discharge path. The parasitic npn bipolar transistor may electrically disconnect input buffer 14 and pad 10 to protect internal circuit 16 of the semiconductor IC chip from the ESD voltage.
In contrast, when the ESD voltage has a negative (−) polarity, a forward connection pn diode (p-type substrate and n+ drain) included in the GGNMOSs may form a discharge path to protect internal circuit 16.
However, the related art ESD protection circuit may be implanted only when all the eight to ten GGNMOSs operate. However, all the GGNMOSs may not operate due to a layout or other factors and failure may occur at a low immunity level.
In the related art ESD protection circuit, since the GGNMOSs use lateral parasitic bipolar operations, the internal circuit of the IC chip may be shocked due to a high voltage before reaching a junction breakdown voltage.